The present invention relates to semiconductor devices. and, more particularly, to semiconductor devices having reduced fringing capacitance between the gate electrode and the source/drain regions.
The requirements for high density performance associated with ultra large scale integration semiconductor devices continue to escalate, thus requiring design features of 0.18 micron and under (e.g., 0.15 micron and under), increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for competitiveness. The reduction of design features to 0.18 micron and under challenges the limitations of conventional semiconductor manufacturing techniques. Moreover, as design features are reduced into the deep sub-micron range, it becomes increasingly difficult to maintain or improve manufacturing throughput for competitiveness.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally doped monocrystalline silicon, and a plurality of interleaved dielectric and conductive layers formed thereon. In a conventional semiconductor device 300, as illustrated in FIG. 3, a p-type substrate 1 is provided with field oxide 2 for isolating an active region comprising N+ source/drain regions 3, and a gate electrode 4, typically of doped polysilicon, above the semiconductor substrate with gate oxide 5 therebetween. Interlayer dielectric 6, typically silicon dioxide, is then deposited thereover and openings formed by conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between a subsequently deposited conductive layer 8, typically aluminum or an aluminum-base alloy, and source/drain regions 3 through contacts 7, and to gate electrode 4. Interlayer dielectric layer 9, typically silicon dioxide, is deposited on conductive layer 8, and another conductive layer 10, typically aluminum or an aluminum-base alloy, is formed on dielectric layer 9 and electrically connected to conductive layer 8 through vias 11.
With continued reference to FIG. 3, conductive layer 10 is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer 12, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer 13 deposited thereon. Protective dielectric layer 13 typically comprises a nitride layer, such as silicon nitride. Alternatively, protective dielectric layer 13 may comprise a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer 13 provides scratch protection to the semiconductor device 300 and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer 13, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer 10 for external connection by means of bonding pad 14 and electrically conductive wires 15 or an external connection electrode (not shown).
Although only two conductive layers 8 and 10 are depicted in FIG. 3 for illustrative convenience, conventional semiconductor devices are not so limited and may comprise more than two conductive layers, depending on design requirements, e.g. five conductive metal layers. Also in the interest of illustrative convenience, FIG. 3 does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
As device features continually shrink in size, various circuit parameters become increasingly important. For example, the capacitance between gate electrode 4 and source/drain regions 3 (i.e., fringing capacitance) is an important parameter that affects circuit operating speeds. Generally, when the transistor is under operating conditions, the voltage on gate electrode 4 changes according to the circuit conditions. This requires charging and discharging the gate electrode 4. Accordingly, any capacitance between gate electrode 4 and source/drain regions 3 slows the charging and discharging, and hence, slows the circuit operating speed.
In conventional semiconductor methodology illustrated in FIG. 4A, after polysilicon gate electrode 4 is formed, ion implantation is conducted, as indicated by arrows 20, to form shallow source/drain (S/D) extensions 22. Subsequent to the formation of the S/D extensions 22, a layer of dielectric material, such as silicon dioxide or silicon nitride is deposited and etched to form insulating sidewall spacers 24 on the side surfaces of gate electrode 4, as shown in FIG. 4B. Adverting to FIG. 4B, ion implantation is then conducted, as indicated by arrows 30, to form moderately-doped source/drain (MDD) or heavily-doped source/drain (HDD) implants 32.
An approach to reducing the fringing capacitance is to increase the distance between the gate electrode 4 and source/drain regions 3. Conventional methodology achieves this goal by increasing the thickness of sidewall spacers 24. This method, however, is not always beneficial because the fringing capacitance will only be decreased if the sidewall spacers 24 are formed prior to implantation. Further, increasing the thickness of sidewall spacers 24 requires additional real estate, which is at a premium in devices having design features of 0.18 micron and under.
A further drawback attendant upon the formation of conventional sidewall spacers 24 is that the material used to form the spacers typically has a relatively high dielectric constant (K), e.g., about 3.9 (oxide) to about 7.0 (nitride). These high-K materials increase the capacitance between gate electrode 4 and S/D extensions 22, thereby slowing circuit operating speeds. It is not practical to employ materials having a low-K to form sidewall spacers, since typical low-K materials are not robust enough to shield shallow S/D extensions 22 from the subsequent impurity implantations forming MDD/HDD implants 32. Further, typical low-K materials are not robust enough to prevent subsequent silicide formations from shorting the gate electrode to the source/drain regions. In high performance integrated circuits, such as those employed in microprocessors, capacitive loading must be reduced to as great an extent as possible to avoid reductions in circuit speed, without sacrificing circuit reliability.
Accordingly, there exists a need for semiconductor devices and a method of manufacturing semiconductor devices exhibiting current high performance and reduced capacitive loading between the gate electrode and source/drain regions (i.e., fringing capacitance) and sidewall spacers having a reduced thickness
An advantage of the present invention is a semiconductor device that exhibits reduced capacitance between the gate electrode and source/drain regions.
Another advantage of the present invention is a semiconductor device having reduced thickness sidewall spacers compared to conventional methodologies.
These and other advantages are achieved by the present invention, wherein a semiconductor device includes recessed source and drain regions that function to reduce capacitance between the gate electrode and source/drain regions, thereby reducing fringing capacitance.
An aspect of the invention is a semiconductor device comprising a semiconductor substrate having a top surface upon which a gate electrode stack is formed. The gate electrode stack includes an upper surface and side surfaces. Doped source/drain regions are recessed into the semiconductor substrate at a first depth that is lower than the main top surface of the semiconductor substrate. The semiconductor device also includes a silicide layer that is formed on the source and drain regions.
The use of recessed source/drain regions provides improved reduction in the fringing capacitance of the semiconductor device. In addition, the thickness of the sidewall spacers need not be increased, as in conventional methodologies, to achieve similar reductions. Accordingly, the size of the semiconductor device the size of the semiconductor device will not necessarily increase because the thickness of the sidewall spacers can remain the same, or even reduced.
Another aspect of the present invention is a method of forming a semiconductor device the method comprising: forming a gate electrode stack on a main surface of a semiconductor substrate, the gate electrode stack having a top surface and side surfaces; forming doped source/drain regions that are recessed into the semiconductor substrate at a first depth that is lower than the main surface of the semiconductor substrate; and forming a refractory layer on the gate electrode stack and the source/drain regions. By forming the source and drain regions at a depth that is lower than the main surface of the semiconductor substrate, fringing capacitance is reduced and performance is increased without sacrificing real estate or reliability.
Additional advantages and novel features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the present invention. The embodiments shown and described provide an illustration of the best mode contemplated for carrying out the present invention. The invention is capable of modifications in various obvious respects, all without departing from the spirit and scope thereof. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. The advantages of the present invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.